Our research

focuses on discovering ways to innovate or improve the efficiency of electrical devices from solar cells to transistors. With more energy-efficient technologies, more power can be produced with less material waste and malfunctions, taking important steps in helping preserve the environment.

Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs

Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (

Abstract: In this work, we investigate the thermal issues of top-gated (TG), ultrathin, atomic layer deposition (ALD) grown, back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by observation and visualization of the self-heating effect (SHE) using high-resolution thermo-reflectance (TR) measurement. SHE is alleviated by highly resistive silicon (HR Si)

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substrate with high thermal conductivity (κSi). The increased temperature (ΔT) of the devices on HR Si substrate is roughly 6 times lower than that with SiO2/Si substrate. Furthermore, thermal simulation with a finite-element method exhibits exceptional agreement to ΔT distribution with experimental results. By thermal engineering, TG In2O3 transistors with channel thickness (Tch) of 1.8 nm and high drain current (ID) up to 2.65 mA/µm are achieved.

Replacing Gallium Arsenide in Space Solar Cells with 2D Materials in a Novel 7-Junction Configuration

Feb. 2022

Abstract: Approximately 3 billion people have never used the internet due to its costs and inaccessibility, particularly in developing countries. To provide these areas with affordable internet, reducing the cost of building and launching satellites has become paramount in the assessment of their design, particularly their solar cells. While three-dimensional

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semiconductor materials like gallium arsenide (GaAs) have been the main material used in these cells to convert solar energy into electrical energy, two-dimensional (2D) materials like tellurene have demonstrated properties that warrant consideration. This research evaluates the potential of a novel 7-junction space solar cell configuration consisting of manganese phosphorus trisulfide, tungsten disulfide, rhenium disulfide, molybdenum disulfide, molybdenum ditelluride, bismuth oxyselenide, and tellurene to replace current 3-junction configurations using GaAs-based materials. Thermodynamic expressions, including the efficiency of a Carnot heat engine and a geometric optimization approach using the Shockley-Queisser triangle, were analyzed to derive equations for two properties critical to a space solar cell: efficiency and specific power. Computational simulations were run, and the results indicate that a 7-junction space solar cell configuration using 2D materials can enable a maximum efficiency gain of 12%, a mass reduction by over one-fifth, and a specific power output improvement of 54% at lower costs compared to GaAs-based space solar cells. The implications of this study point to the performance and cost feasibility of satellite usage for a broad range of applications, with social and environmental significance.

Controlling Threshold Voltage of CMOS SOI Nanowire FETs With Sub-1 nm Dipole Layers Formed by Atomic Layer Deposition

Published in IEEE Transactions on Electron Devices (Vol. 69, No. 2, Feb. 2022,

Abstract: In this article, bidirectional control of threshold voltage ( VT ) is realized in both n- and p-silicon-on-insulator (SOI) nanowire FETs (NWFETs) by using sub-1 nm atomic-layer-deposited (ALD) dipole layers (Y2O3 and Al2O3) for the first time. A 0.7 nm Y2O3 inserted between bottom native SiOx (< 1 nm) and top HfO2 (3 nm) can shift the VTH by −138 and −58 mV for n-

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and p-NWFET, respectively, while 0.7 nm Al2O3 can shift the VT of n-NWFET by +219 mV and p-NWFET by +134 mV. The tunability of such a high-k superstructure for the flat band voltage ( VFB ) shift of capacitors and VTH shift of planar n-SOI FETs are also investigated. Furthermore, to concisely control the VTH and VFB as design, capacitors fabricated with quadra-layer (SiOx/HfO2/Al2O3/Y2O3) high-k superstructure were fabricated and 3 mV VFB shift is achieved by carefully adjusting the composition of intermixed-dipole layers. This work points out the route to concisely tune the threshold voltage of complementary metal-oxide-semiconductor (CMOS) FETs with the desired direction and strength.

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